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Allow setting XSIMD_WITH_SSE3, SSSE3, SSE4_1 and SSE4_2 manually with MSVC - #1430
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… MSVC MSVC doesn't define __SSE3__, __SSSE3__, __SSE4_1__ or __SSE4_2__ even with /arch:SSE4.2. So users need to define these reserved identifiers to enable these instruction sets with MSVC since xtensor-stack#881. But defining them may break other libraries. For example, simdjson >= 5 uses GCC builtins such as __builtin_ctz when __SSE2__ is defined: apache/arrow#51690 This allows users to set XSIMD_WITH_SSE3, XSIMD_WITH_SSSE3, XSIMD_WITH_SSE4_1 and XSIMD_WITH_SSE4_2 manually only with MSVC. For example, users can enable SSE4.2 with MSVC by -DXSIMD_WITH_SSE4_2=1. Lower instruction sets are enabled automatically by the existing MSVC workaround. This also allows selecting SSE3 or SSSE3 with MSVC requested in xtensor-stack#878. Other compilers including clang-cl define these macros based on compiler flags and require the corresponding compiler flags to use intrinsics. So setting them manually with other compilers is reported as an error. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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JohanMabille
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MSVC doesn't define
__SSE3__,__SSSE3__,__SSE4_1__or__SSE4_2__even with/arch:SSE4.2. So users need to define these reserved identifiers to enable these instruction sets with MSVC since #881. But defining them may break other libraries. For example, simdjson >= 5 uses GCC builtins such as__builtin_ctzwhen__SSE2__is defined: apache/arrow#51690This allows users to set
XSIMD_WITH_SSE3,XSIMD_WITH_SSSE3,XSIMD_WITH_SSE4_1andXSIMD_WITH_SSE4_2manually only with MSVC. For example, users can enable SSE4.2 with MSVC by-DXSIMD_WITH_SSE4_2=1. Lower instruction sets are enabled automatically by the existing MSVC workaround. This also allows selecting SSE3 or SSSE3 with MSVC requested in #878.Other compilers including clang-cl define these macros based on compiler flags and require the corresponding compiler flags to use intrinsics. So setting them manually with other compilers is reported as an error.