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Prepare qcom-next based on tag 'Linux 7.3-rc6' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1235
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Salendarsingh Gaud (sgaud-quic) merged 1632 commits intoOct 23, 2026
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Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences are identical to sm8550, but the sub-blocks are not laid out the same way: Nord adds a dedicated USB3_PCS_AON region at offset 0x1e00 and leaves everything else where sm8550 has it. None of the existing offsets tables describe that, so add a v6 table which is the v3 layout plus usb3_pcs_aon. Populating usb3_pcs_aon changes where the driver drives the I/O clamp when entering and leaving autonomous mode: it now uses the real AON region rather than falling back to PCS_MISC, which is what platforms with no AON region do. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-usb-phy-v3-3-68aa02b12b96@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…ntroller Add a compatible for the DWC3 USB controller found on the Qualcomm Nord SoC. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260917-nord-usb-dwc3-dt-v2-1-8f88aa30c434@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…ller The FUSB15201 is an autonomous dual-port USB Type-C and Power Delivery controller. It runs the Type-C state machine and the Power Delivery policy engine on an integrated microcontroller, and exposes only a status and command interface over I2C, so it is not a TCPC. Describe the two ports as addressed connector child nodes, so that a board which wires up only one of them can describe just that one. Assisted-by: LLM Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260916135918.1017527-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The FUSB15201 is a dual-port USB Type-C and Power Delivery controller which runs the Type-C state machine and the PD policy engine on an integrated microcontroller. The host only observes the resulting state and may ask for role swaps, so this is a plain Type-C class driver rather than a TCPC driven by the Type-C Port Manager. Register a Type-C port for each connector described in firmware, report attach and detach, orientation, power and data roles and the PD capability of the partner, and drive the USB role switch of the attached USB controller so that OTG role switching works. Data and power role swaps requested through sysfs are forwarded to the controller, which performs them asynchronously and reports the outcome as a port status interrupt. The controller exposes a per-port VBUS ADC reading, but the Type-C class has no VBUS attribute and nothing needs the value, so it is not read. PD messages, PDOs and alternate modes are not exposed by the hardware at all. The chip-wide MASTER_RESET command would drop both ports at once and has no caller, so it is left alone as well. Assisted-by: LLM Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Link: https://lore.kernel.org/r/20260916135918.1017527-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the base nodes for the three DWC3 USB controllers. These carry only the SoC-invariant properties and are disabled by default. The extension for the embedded Nord variant and relevant board files will add the platform resources and enable them. USB_2 has no SuperSpeed PHY and no 'ss_phy_irq' on this SoC, so it is capped to high-speed and told to use UTMI as its pipe clock. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922-nord-usb-dwc-dts-v2-1-ba2b39f1a843@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the platform resources for the three USB controllers on the embedded Nord variant: clocks, resets, power domains and interconnect paths. Add the eUSB2 PHY for each of the three controllers, plus the QMP combo PHYs for USB_0 and USB_1, and feed the two QMP USB3 pipe clocks back into negcc, which so far carried placeholder zeros in their place. The eUSB2 PHY of instance 2 gets no 'resets': the SoC provides only two QUSB2PHY block resets, belonging to instances 0 and 1. Instance 2 comes out of reset with the rest of the USB20 tile, driven by the controller. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922-nord-usb-dwc-dts-v2-2-ba2b39f1a843@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Describe the RRD USB topology. Enable i2c9 and add the two NXP PTN3222 eUSB2 repeaters for USB_0 and USB_1, supplied from vreg_l3l_1p8 and a new fixed 3.3 V pre-regulator, and reset through pmau0102_i GPIOs 9 and 10. Add the onsemi FUSB15201 Type-C controller at 0x50 with its interrupt and pinctrl state on pmau0102_i gpio8. Unlike RIDE, only port A of the controller is wired on this board, to USB_0, so a single usb-c-connector is described and port B is left out. USB_0 is configured for OTG with usb-role-switch and its HS and SS endpoints are linked to the dwc3 HS endpoint and the QMP combo PHY SS output. USB_1 is a fixed host port feeding an on-board Genesys Logic GL3590 USB 3.1 hub. Add the HS and SS hub pair as children of USB_1, linked with peer-hub, with the HS half reset via TLMM GPIO 170 and the SS half additionally supplied by a fixed 1.2 V rail. Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922-nord-usb-dwc-dts-v2-3-ba2b39f1a843@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Wire up the board specific pieces for USB ports. Enable i2c9 and add the three NXP PTN3222 eUSB2 repeaters (one per USB port) with their 1.8 V supply and reset GPIOs on the PMIC GPIO expanders. Add the onsemi FUSB15201 dual port Type-C controller at 0x50, with its interrupt and pinctrl state on pmau0102_i gpio8. Both controller ports are wired on this board, so describe two usb-c-connector children and cross-link their HS and SS endpoints to the dwc3 HS endpoint and the QMP combo PHY SS output of USB_0 and USB_1. Both controllers therefore run in OTG mode with usb-role-switch. USB_2 has no Type-C connector, so it is configured as a fixed host port. Its VBUS is supplied by a fixed regulator gated by pmau0102_h gpio3, kept always-on since nothing switches it at runtime. Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922-nord-usb-dwc-dts-v2-4-ba2b39f1a843@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Drop WCN regulators which should be added along with WiFi support. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable onsemi FUSB15201 Type-C controller driver which is needed by Qualcomm Nord Ride and RRD reference design boards. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The PCM1681 can use an external system clock supplied on the SCK input pin. Platforms that provide this clock need a way to describe the clock connection in Device Tree. Document the optional 'clocks' and 'clock-names' properties and define the clock name as "sck" to represent the external system clock source. This allows boards using an externally supplied SCK clock to accurately describe the hardware configuration. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260907-nord-asoc-driver-support-v1-2-997d3b20cf43@oss.qualcomm.com
The PCM1681 DAC requires the SCK (system clock) input to be present for proper device operation. On platforms where SCK is provided by a controllable clock source, register accesses over I2C may fail when the clock is not enabled. Add optional clock support to the PCM1681 driver by acquiring the "sck" clock, enabling it during probe, and registering a managed cleanup action to disable it during device removal or probe failure. This allows platforms to model the PCM1681 system clock through the common clock framework and ensures the device is operational before regmap initialization and register accesses occur. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260907-nord-asoc-driver-support-v1-3-997d3b20cf43@oss.qualcomm.com
Document the bindings for the Qualcomm Nord Ride board specific sound card. The bindings are the same as for other newer Qualcomm ADSP sound cards, thus keep them in existing qcom,sm8250.yaml file. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260907-nord-asoc-driver-support-v1-4-997d3b20cf43@oss.qualcomm.com
Add support for the Nord Ride sound card by introducing a new compatible string and associated platform private data. Nord uses external audio codecs with interface requirements that differ from the generic SC8280XP platforms. Add a dedicated hw_params callback to configure the appropriate DAI format for playback and capture streams and to program the codec system clock configuration required by the board. The callback configures the PCM1681 playback path to operate in I2S mode and the ADAU1979 capture path to operate in DSP_A mode. For capture, the ADAU1979 system clock is sourced from LRCLK as required by the hardware design. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260907-nord-asoc-driver-support-v1-5-997d3b20cf43@oss.qualcomm.com
Add the GPR (Generic Packet Router) node to the nord SoC DTSI along with the APM (Audio Process Manager) and PRM (Proxy Resource Manager) audio services. These nodes are required by the Q6APM audio stack to route audio packets between the application processor and the DSP. Assisted-by: LLM Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260914024003.120931-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable audio on the nord RRD board. Add a soundcard node using the qcom,nord-ride-sndcard compatible with two DAI links: - PCM1681 playback over Tertiary MI2S RX - ADAU1979 capture over Tertiary MI2S TX Add MI2S pin mux states (data, SCLK, WS on GPIO 73-76) and the MCLK0 pin state (GPIO 99) to nord-embedded.dtsi so they can be shared with other nord board variants. Add PCM1681/ADAU1979 codec nodes on I2C18, with the PCM1681 system clock supplied via MCLK0. The DAC control lines come off a TCA6408 I/O expander on the same bus, so add that too and hog its dac_enable and click-pop-mute-n outputs, both of which have to be asserted before the DAC produces sound. Assisted-by: LLM Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260914024003.120931-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable audio on the nord-ride-sx board. Add a soundcard node using the qcom,nord-ride-sndcard compatible with two DAI links: - PCM1681 playback over Tertiary MI2S RX - ADAU1979 capture over Tertiary MI2S TX Add PCM1681/ADAU1979 codec nodes on I2C18, with the PCM1681 system clock supplied via MCLK0. The DAC control lines come off a TCA6408 I/O expander on the same bus, so add that too and hog its dac_enable and click-pop-mute-n outputs, both of which have to be asserted before the DAC produces sound. Assisted-by: LLM Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260914024003.120931-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Select SND_SOC_PCM1681 and SND_SOC_ADAU1977_I2C to build the TI PCM1681 DAC and Analog Devices ADAU1977 ADC drivers needed by the nord soundcard. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Document the PCIe PHY found on the Qualcomm Nord platform. Nord has a 32.0 GT/s capable QMP PCIe PHY that can operate in multiple lane configurations using four PHY segments (A/B/C/D). The active topology is selected by firmware through a TCSR configuration register and may be configured as x16, x8+x8, x8+x4+x4, or x8+x4+x2+x2. The binding describes the register regions, clocks, resets, power domains, regulators, PHY provider interface, clock provider interface, and the qcom,link-mode property used by the driver to discover the active lane configuration programmed by firmware. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-1-ed05c6e09240@oss.qualcomm.com
Add the qcom,nord-pcie compatible string to the Qualcomm PCIe controller binding. The Nord PCIe controller is compatible with the SA8775P PCIe controller implementation and reuses the same binding definition. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-2-ed05c6e09240@oss.qualcomm.com
Add the Nord PCIe controller configuration and the platform-specific settings required for correct operation. Nord requires the NO_SNOOP override and L0s to be disabled. It also requires a clock-gating-control (CGC) workaround to address a PCIe power-domain timing-convergence issue. Set the CORE_CLK_CGC_DIS and AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization. The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This behavior is documented in the private QCTDD11972446 erratum, which is not publicly available. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-3-ed05c6e09240@oss.qualcomm.com
…on header qphy_setbits(), qphy_clrbits() and qphy_checkbits() were duplicated verbatim across phy-qcom-qmp-pcie.c, phy-qcom-qmp-pcie-msm8996.c, phy-qcom-qmp-ufs.c, phy-qcom-qmp-usb.c, phy-qcom-qmp-usbc.c and phy-qcom-qmp-combo.c. Move them to the shared phy-qcom-qmp-common.h, which all of these drivers already include, and drop the local copies. This also makes the helpers available to phy-qcom-qmp-pcie-multiphy.c without introducing yet another copy. Suggested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-4-ed05c6e09240@oss.qualcomm.com
Reuse the existing port resource arrays for Glymur register regions, power domains, and NOCSR resets instead of maintaining duplicate Glymur-specific lists. Attach each PHY instance's power domains to the device created for that PHY. This ensures that the associated GDSCs are managed with the lifetime of the individual PHY device rather than the parent multiphy platform device. Validate the clock-output-names property before using its count for allocation, and use a generic module description. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-5-ed05c6e09240@oss.qualcomm.com
Add support for the Nord Gen5x16 bifurcated QMP PCIe PHY. Nord has a single PCIe PHY block split into four ports which can be used in multiple lane configurations: x16, x8+x8, x8+x4+x4 and x8+x4+x2+x2. The active topology is selected through the link mode configuration register, and the driver exposes the corresponding PHY instances based on that mode. Unlike Glymur, where the PHY is initialized by firmware, Nord requires Linux to program the PHY registers. Add the PLL, TXRXZ, PCS and PCS lane initialization tables, along with the required power-up, power-down and soft-reset sequencing. Add per-port and grouped PHY configurations for all supported Nord lane modes. Also add support for regular PHY resets in addition to the NOCSR reset. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-6-ed05c6e09240@oss.qualcomm.com
Neither direction callback clears the opposite buffer: .direction_output() only packs PIN_CONFIG_LEVEL and .direction_input() only packs PIN_CONFIG_INPUT_ENABLE. As pmic_gpio_populate() seeds input_enabled and output_enabled from MODE_CTL, a pad left in DIGITAL_INPUT[_OUTPUT] by the bootloader ends up in DIGITAL_INPUT_OUTPUT whichever direction is requested. That leaves an input still driving the line, and makes pmic_gpio_get_direction() report an output as an input, which breaks consumers that read the direction back: reg-fixed-voltage regulator-wcn-core-vm-1p35: setup of GPIO (default) failed: -1 reg-fixed-voltage regulator-wcn-core-vm-1p35: error -EPERM: can't get GPIO Pack the opposite buffer's PIN_CONFIG_*_ENABLE along with the requested direction, so MODE_CTL becomes DIGITAL_INPUT or DIGITAL_OUTPUT, never both. pmic_gpio_config_set() writes the registers once after walking all configs, so this stays a single write. An open-drain or open-source output is the exception: it only drives one rail, so pmic_gpio_get() needs the input buffer to sample the line rather than return the value last written. Program the input buffer from pad->buffer_type, which gpiolib has already updated via PIN_CONFIG_DRIVE_OPEN_DRAIN, and key pmic_gpio_get_direction() off output_enabled so such pads still read back as outputs. Genuinely bidirectional pads can still be described that way through pinconf; the gpiolib callbacks now mean what gpiolib says they mean. Fixes: 2634475 ("pinctrl: qcom: spmi-gpio: implement .get_direction()") Assisted-by: LLM Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://lore.kernel.org/r/20260927010913.1212600-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Nord has four PCIe controllers backed by a single quadfurcated Gen5 QMP PHY with four ports (A/B/C/D) and a common PCIe SMMU. The ports can be ganged into x16, x8+x8, x8+x4+x4 or x8+x4+x2+x2 topologies; the topology in effect is selected by firmware through the TCSR link-config mode register, which the PHY driver reads at probe time. Describe the x8+x4+x2+x2 topology, i.e. all four controllers usable, as that is the configuration the boards ship with. Add the controller and SMMU nodes to nord.dtsi, and the PHY node along with the per-controller clocks, resets, GDSCs, interconnects, OPP tables and TLMM pin states to nord-embedded.dtsi. The four PCIe pipe clocks also become available now, so hook them up as GCC parents in place of the <0> placeholders. The controllers and the PHY are left disabled here and enabled per board. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The Nord Robotics Reference Design board routes all four PCIe links, so enable pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and describe the PERST# and WAKE# lines of each root port. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…rs and PHY The Nord Ride Embedded board routes all four PCIe links, so enable pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and describe the PERST# and WAKE# lines of each root port. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The Nord Ride Embedded board carries a QCA6797AQ (WCN7850) LGA module on a connectivity adapter card hanging off PCIe2. Two PMIC GPIOs gate the module supplies: PWR_CORE (pmau0102_e GPIO6) enables the DBU_CORE_VL, DBU_CORE_VM and DBU_CORE_VH regulators feeding VDD_CORE_VL/VM/VH, and PWR_CTRL1 (pmau0102_e GPIO8) enables DBU4, which produces the 3.3 V rail. PWR_CTRL2 drives DBU3, which is not populated, so it is left alone. Describe those rails, the WCN7850 PMU that derives the chip supplies from them, and the PCIe endpoint node consuming the PMU outputs. Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-5-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The IQ10 Robotics Reference Design carries a Hamilton (WCN7850) module on a board-to-board connector hanging off PCIe2, using two lanes. Unlike the Ride Embedded board, the RRD generates the module supplies itself rather than relying on the module DBUs: three discrete buck converters produce VDD_CORE_VL, VDD_CORE_VM and VDD_CORE_VH (0.95 V, 1.35 V and 1.95 V), all gated by WLAN0_CORE_PWR_EN on pmau0102_e GPIO6, while the 3.3 V and 1.8 V I/O rails are strapped to the always-on peripheral rails. WLAN0_EN on pmau0102_e GPIO10 releases the module itself. Describe those rails, the WCN7850 PMU that derives the chip supplies from them, and the PCIe endpoint node consuming the PMU outputs. Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-6-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
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… vdda-refgen supplies for PCIe PHYs" A proper upstream change for qref/refgen regulator support on Monaco (QCS8300/SA8775p) platform has been formally reviewed and voted on upstream [1]. The workaround is no longer needed and must be reverted before the proper fix lands to avoid conflicts. This reverts commit 64fbefd. [1] https://lore.kernel.org/all/20260916102023.2054761-3-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Hariharan Sreedhar <hsreedha@qti.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
…f supplies for Monaco" A proper upstream change for qref/refgen regulator support on Monaco (QCS8300/SA8775p) platform has been formally reviewed and voted on upstream [1]. The workaround is no longer needed and must be reverted before the proper fix lands to avoid conflicts. This reverts commit 02d02c1. [1] https://lore.kernel.org/all/20260916102023.2054761-3-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Hariharan Sreedhar <hsreedha@qti.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
…nd SA8775p The PCIe QMP PHYs on Monaco (QCS8300) require stable reference voltage provided by refgen and reference clock provided by qref. The refgen and qref require power supplies. Add a new sa8775p_qmp_phy_vreg_l list with vdda-qref and vdda-refgen supplies, and use it for qcs8300_qmp_gen4x2, sa8775p_qmp_gen4x2 and sa8775p_qmp_gen4x4 PCIe PHY configurations Link: https://lore.kernel.org/all/20260916102023.2054761-3-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Signed-off-by: Hariharan Sreedhar <hsreedha@qti.qualcomm.com>
The QREF block supplies reference clocks to PCIe/USB/UFS PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on x1e80100. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. These LDOs are required by QREF to provide a stable reference clock, without which the USB/PCIe/eDP PHYs cannot work properly, so the supplies are marked required even though it breaks ABI. TCSR does not act as a reset provider on x1e80100: no driver has ever registered a reset controller for it, and no consumer references it as a reset, so #reset-cells is dropped entirely rather than documented. Add a dedicated binding file for qcom,x1e80100-tcsr and document the supply properties. Link: https://lore.kernel.org/all/20260827-hamoa_tcsr_qref_0826-v4-1-663c9d30468d@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the x1e80100 driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Link: https://lore.kernel.org/all/20260827-hamoa_tcsr_qref_0826-v4-2-663c9d30468d@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…ement support" This change regresses the audio test case on all soundiwre based tagets. Revert this for fixing the issue in soundwire where IRQ registers two times. This reverts commit ea24938. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…pport Add the SoundWire core and Qualcomm controller changes required for SDCA codec topologies and for Qualcomm SoCs that combine two controller instances to expose additional data lanes. Core stream changes: - Allow a Slave to contribute more than one port to the same stream across multiple sdw_stream_add_slave() calls. Ports are now always appended to port_list and the pre-call count is used so port configuration only fills in newly added entries instead of overwriting those from earlier calls. - Preserve per-port port_params.bps pre-set by compute_params() and only fall back to the stream-wide value when it was left at zero, so a single stream can carry ports with different wire widths. - Explicitly set port_params.num so master port_params callbacks always receive the correct port number. Qualcomm controller changes: - Add the optional qcom,ports-ch-mask property to fix the per-port channel mask where the stream derived value is insufficient, such as a wired stereo PDM port opened by a mono PCM stream. - Gate the additional DIN PCM port control register for ports that belong to a PCM stream, as required by SDCA class compliant slaves. - Implement the lane provider role, where a controller declaring #qcom,swrm-lane-cells is brought up as a data only lane source and does not register a SoundWire bus of its own. - Implement the lane consumer role, where qcom,secondary-lanes resolves a provider at probe time and deferred probe is used until the provider is ready. Per-port DPn register accesses that land on a borrowed lane are translated and routed to the provider, and the port lane selector is converted to provider local numbering. - Program MM_SYNC on both controllers of a multi-master pair so their frame generators lock to a single SWR_CLK, and re-apply it on resume since it does not survive a bus clock stop. - Program the frame control SSP period derived from the current frame geometry on v3.1.0+ parts, both at init and on every bank switch, and clear CLK_DIV in the same place. - Fan broadcast SCP_FrameCtrl writes out to per-slave unicasts on a multi-master pair, where the hardware broadcast is not acted upon by the slaves. Bus changes: - Iterate every string in a slave node compatible property when matching the SoundWire class ID, so a vendor variant compatible can precede the class ID compatible. Non-multilane platforms are unaffected: without qcom,secondary-lanes no provider is resolved and all register accesses keep using the existing paths. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
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The GPR bus needs to make response callbacks available before invoking a client probe because clients can issue synchronous commands from probe. This creates a short interval where a callback can run before the client has published its private data. Make q6apm publish its driver data only after all callback-visible state has been initialized. Have the q6apm and q6prm callbacks ignore packets received before driver data is available. Fixes: ec1471a ("soc: qcom: apr: Add GPR support") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20261022144130.2443667-2-mohit.sharma@oss.qualcomm.com/ Co-developed-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Mohit Sharma <mohit.sharma@oss.qualcomm.com>
A GPR service driver can issue synchronous commands from its probe path, or populate child devices which issue commands before the parent probe returns. The APR/GPR bus currently installs the GPR service callback only after the service driver's probe has completed. If a response arrives while the client probe is still running, GPR finds the destination service but cannot dispatch the response because the service callback is NULL. The client waiting for the response eventually times out. This was observed intermittently on Qualcomm Lemans and Monaco platforms when q6apm child probing sent an APM shared-memory map command before the parent probe returned. The failure has the following signature: qcom-apm ... CMD timeout for [100100c] opcode q6apm-dai ... Audio Start: Buffer Allocation failed rc = -110 snd-sc8280xp ... ASoC: can't create pcm MultiMedia1 Playback :-110 Install the GPR callback before invoking the client probe so responses to probe-time commands can be dispatched. Clear the callback again if probe fails, and preserve the existing callback ordering for APR clients. Fixes: ec1471a ("soc: qcom: apr: Add GPR support") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20261022144130.2443667-3-mohit.sharma@oss.qualcomm.com/ Co-developed-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Mohit Sharma <mohit.sharma@oss.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Komal Bajaj (Komal-Bajaj)
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
Salendarsingh Gaud (sgaud-quic)
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Name SHA Commits
tech/bsp/clk 8fbbeee 20
tech/bsp/devfreq 0837ca4 7
tech/bsp/interconnect 81fc6e2 1
tech/bsp/sched 2cb2e18 2
tech/security/firmware-smc 16b0235 9
tech/bsp/soc-infra 3633b44 39
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 8c716bc 1
tech/bus/peripherals d69a417 8
tech/bus/pci/all 9189a06 42
tech/bus/usb/dwc 6f24600 8
tech/bus/usb/phy b94824d 38
tech/debug/hwtracing fae0f79 27
tech/pmic/misc 0adc32c 19
tech/mem/iommu e1fac89 11
tech/mm/audio/all 277113f 37
tech/mm/camss dd65494 39
tech/mm/drm 55b9133 164
tech/mm/fastrpc fab5742 4
tech/mm/video bbe1a02 57
tech/mm/gpu e065d5a 1
tech/net/ath 722be84 7
tech/net/eth 7151807 19
tech/net/bluetooth e352848 8
tech/pm/pmdomain 16a7451 3
tech/pm/power 3faa52e 14
tech/pm/thermal 2602b17 9
tech/security/crypto 4c71afd 13
tech/security/ice dc34f45 14
tech/security/optee-next 9babb9a 1
tech/storage/all f2a8c9a 9
tech/all/dt/qcs6490 fdf8383 21
tech/all/dt/qcs9100 df4f38e 23
tech/all/dt/qcs8300 6a513e3 28
tech/all/dt/qcs615 4bc8635 14
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza fd76dfc 18
tech/all/dt/hamoa 7cdc1c1 39
tech/all/dt/glymur a619ea6 33
tech/all/dt/kaanapali b395c11 18
tech/all/dt/pakala 9cdd195 13
tech/all/hawi 17d1dc3 40
tech/all/maili c7b7e74 9
tech/all/shikra fc6960a 206
tech/all/config 4dfbba1 89
tech/overlay/dt e3a5bec 99
tech/all/workaround ebc9406 14
tech/noup/debug/all 9f1e8ae 37
tech/hwe/unoq a2d85fe 4
early/hwe/nord 9d5b3c8 120
early/hwe/staging/nord b84ee15 127
tech/mem/dma-buf f153776 1
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