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feat(P1): revision-aware ESP32-P4 dual-silicon firmware provisioning preview - #352
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…ROM probe Keep immutable legacy v1 support, validate and hash two non-overlapping revision images, select v3.2 candidate only on actual ROM evidence, and rehash before write.
…alog Use maintained IDF 5.5.6, preserve v1 legacy manifest, compile v3.x from isolated defaults and SDKCONFIG, validate merged image revision headers and source SHA, ship v3.2 engineering preview only.
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…pin postboot board identity Add 300s monotonic Qt transaction deadline, ACK-verified STOP preflight, and exact board/boot continuity verification. Make running-test interruption visible in primary dialog.
…sical flash offsets ESP32-P4 uses 0x2000 second-stage bootloader and default 0x10000 factory app. Fail closed when either disagrees with qualified pre-v3 or v3.2 catalog.
…o selection regression
… identities Require unambiguous espflash ROM MAC; block wrong board before write and require same physical device after reset even for blank boards. Add MAC parser negatives and correct IDF provenance.
…y catalog qualification Prevent retry from bypassing SV/PTP STOP, pin last ROM identity across failed attempts, require lab-board acknowledgement for blank boards, reject contradictory chip probe and prohibit unqualified v3 stable catalogs.
…te for blank-board firmware setup
…board-info output
…eering preview Reuse same-workflow exact-HEAD firmware artifact from Windows Native Preview without another IDF build. Stage two verified images, provenance and pinned espflash into Linux AppImage; smoke extracted AppImage with production firmware contract; preserve stable tag flow and standalone GUI-only CI.
…eusable preview builder Use one shared exact-head AppImage builder for paired preview and stable tag builds; move stable uploader behind separately authorized workflow_dispatch. Keep existing published-release auto-dispatch path and immutable historical tags protected.
…sh cancellation Prevent QProcess timeout from releasing COM lease before worker exit; close the discovery ownership loophole; add deterministic timeout/port-retirement regression and concise v1.3/v3.2 physical acceptance guide.
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Engineering-preview software acceptance — COMPLETE (physical qualification pending)
Merged design baseline: PR #351 (PRD, ARD, AGENTS). This PR implements working C++ Studio provisioning and a matched dual-silicon ESP-IDF firmware pipeline without changing immutable M3.H.3 official stable assets.
Production changes
--force, auto-flash at startup, auto-START SV/PTP or invent rollback.Exact-head software evidence
Reviewed PR HEAD:
75b16341ac1f56f8b2ed6c0a560edc406a9a818e.All applicable workflows completed successfully on this exact SHA: firmware injector, Qt and deterministic S8 session harness, C++ CI (Linux gcc/clang, Windows MSVC), Windows Lifecycle, Security and Evidence, CI Routing Policy, Product Naming Guard, Public Documentation Navigation, standard Linux AppImage and ARStack Studio Native Preview. The stable-release attachment job was intentionally skipped for this pull request, not counted as a pass.
espflash v4.5.0, extracted AppImage firmware contract smoke PASS.Hardware evidence and release gate
ESP32-P4 v3.2 remains an UNVERIFIED PHYSICAL ENGINEERING PREVIEW, not stable or production-qualified. Pinned Rust
espflash v4.5.0is packaged and software-checked but actual USB flashing, v3.2 boot, Ethernet PHY, 4I+4V 4000fps SV and PTP capture and interrupted-write recovery still require real v3.2 hardware, plus regression on v1.3. See P1 Physical HIL Acceptance. No physical PASS/UTC traceability claims.Open #330 LAN autonomy and #350 M4 roster remain separate; no rebasing/cherry-picking them. Documentation approval #351, PR #352 merged only as physically unqualified engineering preview.
Safety release invariant: historical M3.H.3 stable tag and its seven assets unchanged.