P0: enforce shared IEC 61850-9-3 PTP SOURCE profile before START; truthful toggle by masarray · Pull Request #265 · masarray/arstack61850

feat(ptp): shared IEC/IEEE 61850-9-3 SOURCE cadence admission for Studio and firmware

masarray

committed

afd4250

fix(ptp): fail preflight locally on mismatched 61850-9-3 SOURCE profile, before issuing serial commands

masarray

committed

4ff9cd3

fix(studio): enforce SOURCE profile contract and display PTP STARTING without misleading toggle bounce

masarray

committed

7a3e862

ux(studio): amber PTP switch pending state, green only for real board RUNNING

masarray

committed

518e227

feat(ptp): expose compact read-only profile-rejection reason

masarray

committed

597c4d0

fix(ptp): classify profile admission failures without changing time-critical PTP/SV

masarray

committed

795bea4

fix(ptp): report actual firmware configuration rejection code to Studio

masarray

committed

d822728

fix(ptp): PTPROLE rejection uses firmware-owned cause

masarray

committed

25818c3

test(studio): reject SOURCE Pdelay/cadence mismatch before PTP serial state machine

masarray

committed

24c64db

test(ptp): confirm identical portable 9-3 admission from scalar Studio and runtime options

masarray

committed

2908e7f

test(studio): guard stable switch and board-specific PTP configuration causes

masarray

committed

654dd42

test(studio): update advanced PTP profile contract for explicit SOURCE role parameter

masarray

committed

836c881

ux(studio): preserve amber PTP STARTING intent in both Main tray and Advanced, no immediate switch snapback

masarray

committed

0835dae

ux(ptp): lock SOURCE cadence to 1s in standard Studio profile; keep core/backend validation for direct calls

masarray

committed

ef4de7a

test(studio): standard SOURCE cannot accidentally send nonstandard hidden cadence

masarray

committed

ce5ffac

ux(ptp): hide SOURCE-only non-editable timing fields, show one true 9-3 profile summary

masarray

committed

df73fea

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P0: enforce shared IEC 61850-9-3 PTP SOURCE profile before START; truthful toggle - #265

P0: enforce shared IEC 61850-9-3 PTP SOURCE profile before START; truthful toggle#265
masarray wants to merge 16 commits into
fix/p0-ptp-start-firmware-provenance-20261020from
fix/p0-ptp-profile-contract-20261020

Commits on Oct 20, 2026

feat(ptp): shared IEC/IEEE 61850-9-3 SOURCE cadence admission for Studio and firmware

fix(ptp): fail preflight locally on mismatched 61850-9-3 SOURCE profile, before issuing serial commands

fix(studio): enforce SOURCE profile contract and display PTP STARTING without misleading toggle bounce

ux(studio): amber PTP switch pending state, green only for real board RUNNING

feat(ptp): expose compact read-only profile-rejection reason

fix(ptp): classify profile admission failures without changing time-critical PTP/SV

fix(ptp): report actual firmware configuration rejection code to Studio

fix(ptp): PTPROLE rejection uses firmware-owned cause

test(studio): reject SOURCE Pdelay/cadence mismatch before PTP serial state machine

test(ptp): confirm identical portable 9-3 admission from scalar Studio and runtime options

test(studio): guard stable switch and board-specific PTP configuration causes

test(studio): update advanced PTP profile contract for explicit SOURCE role parameter

ux(studio): preserve amber PTP STARTING intent in both Main tray and Advanced, no immediate switch snapback

ux(ptp): lock SOURCE cadence to 1s in standard Studio profile; keep core/backend validation for direct calls

test(studio): standard SOURCE cannot accidentally send nonstandard hidden cadence

ux(ptp): hide SOURCE-only non-editable timing fields, show one true 9-3 profile summary