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P3-A1.1: live SV signal control without realtime stream rebuilds #42

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Description

@masarray

Goal

Deliver the user workflow import SCL -> validate/configure stream -> enter initial values -> START -> change values while RUNNING -> STOP while preserving deterministic publication and canonical stream identity.

This issue is vendor-neutral. No commercial product names or manufacturer-specific runtime branches belong in the implementation.

Runtime contract

Separate immutable profile state from mutable live signal state.

Immutable while RUNNING:

  • destination MAC / APPID / VLAN / PCP;
  • svID / DataSet-field policy / confRev / nofASDU;
  • publisher rate / sample mode / validated counter policy;
  • ordered payload layout and optional ASDU-field policy.

Mutable while RUNNING:

  • per-channel magnitude/raw wire-count target;
  • per-channel phase;
  • signal frequency where supported;
  • quality values;
  • enable/disable and later scenario/fault state.

Profile changes require STOP/re-arm. Live signal changes commit coherently at a sample boundary and do not reset smpCnt or rebuild BER.

Realtime architecture

  • control plane writes a complete next SvLiveSignalState generation;
  • coherent snapshot publication with bounded atomic/seqlock semantics;
  • realtime publisher copies one generation at the start of a sample;
  • fixed-point phase accumulator + precomputed sine LUT; no floating-point work in the hot sample loop;
  • payload value and quality fields are patched into prebuilt templates;
  • signal frequency is independent from publisher event rate;
  • START requests a clean phase/sample-counter restart;
  • STOP suppresses transmission without destroying the validated profile.

Development transport

First bench implementation may use the existing serial console for START, STOP, SHOW, SET, FREQ, QUALITY, ENABLE, and ZERO. This is a temporary test transport only. The final product will use a versioned bounded host/device control protocol and desktop UI with the same realtime state model.

Acceptance

  • compile and regression-test coherent live state generations;
  • start with a valid 4I+4V development profile;
  • change at least two channels while RUNNING and observe the new values without malformed frames or sequence restart;
  • change signal frequency while RUNNING with continuous phase accumulator;
  • update quality while RUNNING;
  • STOP suppresses canonical TX; START restarts from defined phase/counter state;
  • hot path contains no XML/text parsing, heap allocation, BER rebuild, logging, or host-facing mutex;
  • later converge with P3-A1: compiled SV device profile and deterministic ESP32-P4 activation #36 compiled device profiles and PTP: fix ESP32-P4 hardware TX timestamp pair count #26 hardware TX timestamps.

Initial architecture notes are in docs/LIVE_INJECTION_WORKFLOW.md and docs/LIVE_INJECTION_STATE_MACHINE.md.

Activity

  1. masarray commented on Oct 23, 2026

    @masarray
    OwnerAuthor

    2026-10-23 operator-reported Live Setpoint issue: committing a Voltage/Current cell via Enter/Tab/focus-out left the waveform unchanged until manual Apply Live or STOP/START. Fix implemented in consolidation Draft PR #286 HEAD 042df0d40ddd3f061ebeebc81c662c585827e346: 40 ms event-turn coalescer sends a complete 4I4V atomic CFG transaction (firmware ACK + readback), queues newer revisions while previous CFG in flight, keeps RUNNING editors enabled, frequency commits only on edit-finished, and removes manual Apply Live UI. Board SV/PTP codec/clock firmware files unchanged. Baseline field-tested version preserved at checkpoint/sv-ptp-digsub-auto-7s-20261023 / 73c97272.... Exact-head Windows Preview CI and hardware live-edit evidence remain pending; please keep this issue OPEN until on-wire IA/UA change is confirmed with no STOP, no counter reset and maintained DigSub auto sync.

  2. masarray commented on Oct 23, 2026

    @masarray
    OwnerAuthor

    Team coordination / release gate 2026-10-23. The concurrent Studio AUTO-LIVE lane has an exact-head software build PASS at #286 042df0d40ddd3f061ebeebc81c662c585827e346 via Native Preview 39882032904. Enter/Tab/focus-out now schedules a bounded coalesced atomic 4I4V CFG transaction; updated edits drain after ACK and there is no manual Apply Live requirement. This is a software milestone for the live setpoint portion of #42, NOT issue completion. Remain OPEN pending hardware IA/UA change while RUNNING, captured before/after RMS/angle/quality, uninterrupted smpCnt and 4000fps, no PTP rearm, no STOP/START, and confirmed device hash/readback. Existing immutable profile/runtime invariants and issue #36 profile convergence remain in scope. The other thread owns live QML; cleanup lane changes no QML.

  3. masarray commented on Oct 23, 2026

    @masarray
    OwnerAuthor

    P0 AUTO-LIVE acceptance correction · 2026-10-23

    Do not release against #286 042df0d4: its matched package exhibited loss of SV reception in ARSAS/DigSubAnalyzer on the user's hardware. Earlier 35s/140,271-frame ~7s AUTO capture was from 7c95f70c, NOT the subsequent #286 build. This invalidates any assumption that software-only Auto-Live CI success proves no physical regression.

    Current verified source-recovery lane: Draft PR #288 based on captured-source 7c95f70c, with automatic Enter/Tab/focus-out whole-4I4V CFG + operator tests and limited workflow changes; firmware/PTP/COM production runtime source unchanged from the captured source. Physical correctness of rebuilt image remains unverified. Native Preview firmware job PASS at reviewed 90e2755f, Windows preview not yet completed at audit.

    Issue #42 remains OPEN, P0 physical release blocker: require verified flashed buildId; 30s unedited 4kfps capture accepted by ARSAS+DigSubAnalyzer; then IA, UA and frequency committed while RUNNING with token/hash/readback and captured actual RMS/phase/quality change, no transient partial channel state, no PTP SOURCE reset, no SV STOP/START or smpCnt break, then repeated editing and long-run stability. Compare against captured 7c95 baseline; preserve exact image/PCAP/log evidence. This is not mere UI-button removal.

  4. masarray commented on Oct 23, 2026

    @masarray
    OwnerAuthor

    P0 AUTO-LIVE reconnect authority QA (2026-10-23)

    Code audit of current recovery Draft #288 at 90e2755f found an unresolved authorization difference from #253: QML schedules automatic 4I4V CFG upon verified+RUNNING, while liveControlReady() treats observed board RUNNING as sufficient. On reconnect, an existing board RUNNING state is not the same as a START approved in the current Studio session. onDeviceVerifiedChanged() clears pending queued edits but does not establish a lasting disarmed live-edit state. This is potential unsolicited CFG after a new edit, not yet reproduced as a physical bug.

    Required before closing #42: prove current-boot, session-generation and START-token-bound live-edit arm/disarm; no CFG on unsolicited RUNNING after USB reconnect or board reset; no replay of saved drafts; deliberate re-arm/adoption requires explicit operator action. Positive test must preserve instant Enter/Tab/focus-out eight-channel commit during normal verified RUNNING with ACK/readback, no STOP/START/smpCnt break. Negative tests: reconnect while SV RUNNING, boot change, port loss during apply, stale late ACK. Full rationale and line-level source reference: #288 (comment) .

    Keep PR #253 OPEN for this unique semantic gate. Cleanup thread made no source/code changes.

  5. masarray commented on Oct 23, 2026

    @masarray
    OwnerAuthor

    2026-10-23 status correction: old manual Apply Live field defect and new checkpoint

    Operator's original 7c95f70c pair shows QML UA draft 20V while on-wire signal remained ~1000 raw counts = 10V (100 counts/V), manual Apply Live button still visible. Captured 490,881 decodable SV includes a 2.359893s STOP/START gap, which must not be labeled live no-drop editing. Team's #288 recovery replaces manual button with QML coalesced auto transaction and corrects interrupted-capture partial reporting; merged to isolated checkpoint/sv-ptp-autolive-capture-ci-merged-20261023, not main. Final software CI at 8a24285 all five key workflows PASS; rebuilt image not physically verified after 20V GUI edit.

    Still OPEN: demonstrate firmware hash/buildId, actual UA 10→20V, IA amplitude/phase and frequency committed on Enter/blur while publisher continues same SV session, CFG ACK/readback, no STOP/START/clock/PTP reset/smpCnt disruption, plus 10× edits and soak; inspect active reconnect/RUNNING-without-new-operator-START authorization risk in recovered current QML (prior source audit #288 comment still applicable at final head). Keep original #253 source PR OPEN until semantics reconciled; no unsafe automatic reconnect replay.

  6. masarray commented on Oct 24, 2026

    @masarray
    OwnerAuthor

    M3.H release backlog reconciliation — 2026-10-24

    Post-M3.H feature disposition: old PR #253 (atomic RUNNING 4I+4V scenario snapshot, nonce/checksum ACK/readback, STOP safety) closed as superseded historical source, NOT merged and NOT validated. This issue remains open for a fresh main-based implementation with on-wire atomicity, no mixed intermediate frames, no smpCnt reset, negative ACK/replay tests, and paired ESP32-P4 firmware/Studio CI.

    Canonical ledger: https://github.com/masarray/arstack61850/blob/main/docs/integration/M3H_MAINLINE_RELEASE_SOURCE_CLOSURE_2026-10-24.md .

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