Fix batched GEMM guards, Fortran arguments and empty batches

[BenKnill]

Fixes #6121.

Submitting the proposed two-file implementation patch following @martin-frbg's request. The implementation diff is unchanged from the issue and is based on develop at 6d8c8801.

• Batched small-matrix dispatch now uses ordinary GEMM's existing scalar guard and GEMM_SMALL_MATRIX_PERMIT, avoiding the alpha-zero NaN propagation and the unsupported BF16 small-kernel route.
• The Fortran interfaces associate TRANSA with A and TRANSB with B, and grouped Fortran batches pass a_array as A and b_array as B. The CBLAS row-major mapping is unchanged.
• Strided batches return before dispatch when M or N is zero. All members share those dimensions.

Validation

Compared unpatched 6d8c8801 with the same library sources plus this fix. Builds used LP64, NOFORTRAN=1, NO_LAPACK=1, and BF16 support. The C-implemented Fortran ABI entry points were exercised; no Fortran compiler or Fortran-language caller was used.

Configuration	Issue's exact-result checker	Wider probes after the fix
x86-64 HASWELL, threaded build	0/4 to 4/4 passing	40/40 batched cases across S/D/C/Z/SB; 210/210 double-precision GEMM, batch and triangular cases
ARM64 DYNAMIC_ARCH under QEMU, 14 dispatch selections	0/4 to 4/4 on each	40/40 batched cases on each; the 210-case probe passes on 13 selections, with the ARMV9SME caveat below
ARM64 Linux guest on Apple M5, automatic dispatch, NEOVERSEN1 and ARMV8	0/4 to 4/4 on each	40/40 and 210/210

The first-call M=0 crash is absent after the fix. Alpha-zero edge probes at sizes up to and across the old small-matrix threshold also pass.

The existing unit tests passed on x86 (141 core tests) and ARM64 NEOVERSEN1 under QEMU and on the M5 guest (143 core tests), including all 1,502 pre-existing extension tests. The x86 unit suites were also run with four threads. Validation used a local checkout containing an additional test-only commit; that commit does not change library sources and is not included in this PR. The fix-only commit was not separately rebuilt.

QEMU caveat: with forced ARMV9SME at VL128, eight ordinary cblas_dgemm control cases in the wider probe fail on both the unpatched and patched trees, and also on the earlier 33746423 baseline. All exercised batched cases pass after the fix, but the unmodified aggregate ARM validator remains FAIL (two failing invocations among 280 records, baseline and patched). The control discrepancy has not been diagnosed as an emulator or hardware/kernel issue.

The probes force one runtime thread; the four-thread unit runs do not establish parallel batched-dispatch coverage. No real SVE/SME hardware, additional SVE lengths, ILP64, LAPACK-enabled, CMake, macOS, or GitHub CI validation is claimed.

Found through AI-assisted code review and differential testing by the GPT-6.1 Sol noninterference lane, coordinated and independently reproduced by Opus 5.5. GPT-6 Astra and Opus 5.5 prepared and validated the fix.

[martin-frbg]

Thank you