Add RISCV64_ZVL1024B (wide VLEN / SpacemiT K3 A100)

Makefile.prebuild

@@ -63,6 +63,9 @@ ifeq ($(TARGET), x280)
 TARGET_FLAGS = -march=rv64imafdcv_zba_zbb_zfh -mabi=lp64d
 endif
 
+ifeq ($(TARGET), RISCV64_ZVL1024B)
+TARGET_FLAGS = -march=rv64imafdcv -mabi=lp64d
+endif
 ifeq ($(TARGET), RISCV64_ZVL256B)
 TARGET_FLAGS = -march=rv64imafdcv -mabi=lp64d
 endif

Makefile.riscv64

@@ -13,6 +13,10 @@ endif
 ifeq ($(BUILD_BFLOAT16), 1)
 RISCV64_OPT := $(RISCV64_OPT)_zvfbfwma
 endif
+ifeq ($(CORE), RISCV64_ZVL1024B)
+CCOMMON_OPT += -march=$(RISCV64_OPT)_zvl1024b -mabi=lp64d
+FCOMMON_OPT += -march=$(RISCV64_OPT) -mabi=lp64d
+endif
 ifeq ($(CORE), RISCV64_ZVL256B)
 CCOMMON_OPT += -march=$(RISCV64_OPT)_zvl256b -mabi=lp64d
 FCOMMON_OPT += -march=$(RISCV64_OPT) -mabi=lp64d

Makefile.system

@@ -783,6 +783,7 @@ ifeq ($(ARCH), riscv64)
 DYNAMIC_CORE = RISCV64_GENERIC
 DYNAMIC_CORE += RISCV64_ZVL128B
 DYNAMIC_CORE += RISCV64_ZVL256B
+DYNAMIC_CORE += RISCV64_ZVL1024B
 ifdef DYNAMIC_LIST
 override DYNAMIC_CORE = RISCV64_GENERIC $(DYNAMIC_LIST)
 XCCOMMON_OPT = -DDYNAMIC_LIST -DDYN_RISCV64_GENERIC

README.md

@@ -223,7 +223,7 @@ Please read `GotoBLAS_01Readme.txt` for older CPU models already supported by th
 
 (For RVV 1.0 target selection and compiler requirements, see the [RISC-V section in docs/install.md](docs/install.md#risc-v).)
 
-- **ZVL???B**: Level-3 BLAS and Level-1,2 including vectorised kernels targeting generic RISCV cores with vector support with registers of at least the corresponding width; ZVL128B and ZVL256B are available.
+- **ZVL???B**: Level-3 BLAS and Level-1,2 including vectorised kernels targeting generic RISCV cores with vector support with registers of at least the corresponding width; ZVL128B, ZVL256B, and ZVL1024B are available.
 e.g.:
   ```sh
     make TARGET=RISCV64_ZVL256B CFLAGS="-DTARGET=RISCV64_ZVL256B" \
@@ -233,6 +233,14 @@ e.g.:
     HOSTCC=gcc HOSTFC=gfortran -j
   ```
 
+  ```sh
+    make TARGET=RISCV64_ZVL1024B CFLAGS="-DTARGET=RISCV64_ZVL1024B" \
+    BINARY=64 ARCH=riscv64 CC='clang -target riscv64-unknown-linux-gnu' \
+    AR=riscv64-unknown-linux-gnu-ar AS=riscv64-unknown-linux-gnu-gcc \
+    LD=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran \
+    HOSTCC=gcc HOSTFC=gfortran -j
+  ```
+
 #### LOONGARCH64
 
 - **LA64_GENERIC**: Optimized Level-3, Level-2 and Level-1 BLAS with scalar instruction

TargetList.txt

@@ -128,6 +128,7 @@ RISCV64_ZVL128B
 C910V
 x280
 RISCV64_ZVL256B
+RISCV64_ZVL1024B
 U74 (e.g. SiFive U74 / StarFive JH7110 / VisionFive 2)
 
 11.LOONGARCH64:

cmake/arch.cmake

@@ -80,7 +80,7 @@ if (DYNAMIC_ARCH)
   endif ()
 
   if (RISCV64)
-	  set(DYNAMIC_CORE RISCV64_GENERIC RISCV64_ZVL128B RISCV64_ZVL256B) 
+	  set(DYNAMIC_CORE RISCV64_GENERIC RISCV64_ZVL128B RISCV64_ZVL256B RISCV64_ZVL1024B) 
   endif ()
 
   if (X86)

cmake/cc.cmake

@@ -410,14 +410,17 @@ if (${CORE} STREQUAL PPCG4)
 endif ()
 
 
-if ((${CORE} STREQUAL RISCV64_ZVL128B) OR (${CORE} STREQUAL RISCV64_ZVL256B))
+if ((${CORE} STREQUAL RISCV64_ZVL128B) OR (${CORE} STREQUAL RISCV64_ZVL256B) OR (${CORE} STREQUAL RISCV64_ZVL1024B))
   set (RISCV64_OPT "rv64imafdcv")
   if (BUILD_BFLOAT16)
     set (RISCV64_OPT "${RISCV64_OPT}_zvfbfwma")
   endif()
   if (BUILD_HFLOAT16)
     set (RISCV64_OPT "${RISCV64_OPT}_zvfh_zfh")
   endif()
+  if (${CORE} STREQUAL RISCV64_ZVL1024B)
+    set (CCOMMON_OPT "${CCOMMON_OPT} -march=${RISCV64_OPT}_zvl1024b -mabi=lp64d")
+  endif()
   if (${CORE} STREQUAL RISCV64_ZVL256B)
     set (CCOMMON_OPT "${CCOMMON_OPT} -march=${RISCV64_OPT}_zvl256b -mabi=lp64d")
   endif()

cmake/prebuild.cmake

@@ -1468,6 +1468,24 @@ endif ()
     set(ZGEMM_UNROLL_M 4)
     set(ZGEMM_UNROLL_N 4)
     set(SYMV_P 16)
+  elseif ("${TCORE}" STREQUAL "RISCV64_ZVL1024B")
+    file(APPEND ${TARGET_CONF_TEMP}
+      "#define L1_DATA_SIZE 65536\n"
+      "#define L1_DATA_LINESIZE 32\n"
+      "#define L2_SIZE 2097152\n"
+      "#define L2_LINESIZE 32 \n"
+      "#define DTB_DEFAULT_ENTRIES 128\n"
+      "#define DTB_SIZE 4096\n"
+      "#define L2_ASSOCIATIVE 4\n")
+    set(SGEMM_UNROLL_M 16)
+    set(SGEMM_UNROLL_N 8)
+    set(DGEMM_UNROLL_M 16)
+    set(DGEMM_UNROLL_N 8)
+    set(CGEMM_UNROLL_M 8)
+    set(CGEMM_UNROLL_N 8)
+    set(ZGEMM_UNROLL_M 8)
+    set(ZGEMM_UNROLL_N 4)
+    set(SYMV_P 16)
   elseif ("${TCORE}" STREQUAL "RISCV64_ZVL256B")
     file(APPEND ${TARGET_CONF_TEMP}
       "#define L1_DATA_SIZE 65536\n"

cmake/system.cmake

@@ -392,14 +392,17 @@ if (${TARGET} STREQUAL NEOVERSEV1)
     endif()
   endif()
 
-  if ((${TARGET} STREQUAL RISCV64_ZVL128B) OR (${TARGET} STREQUAL RISCV64_ZVL256B))
+  if ((${TARGET} STREQUAL RISCV64_ZVL128B) OR (${TARGET} STREQUAL RISCV64_ZVL256B) OR (${TARGET} STREQUAL RISCV64_ZVL1024B))
     set (RISCV64_OPT "rv64imafdcv")
     if (BUILD_BFLOAT16)
       set (RISCV64_OPT "${RISCV64_OPT}_zvfbfwma")
     endif()
     if (BUILD_HFLOAT16)
       set (RISCV64_OPT "${RISCV64_OPT}_zvfh_zfh")
     endif()
+    if (${TARGET} STREQUAL RISCV64_ZVL1024B)
+      set (KERNEL_DEFINITIONS "${KERNEL_DEFINITIONS} -march=${RISCV64_OPT}_zvl1024b -mabi=lp64d")
+    endif()
     if (${TARGET} STREQUAL RISCV64_ZVL256B)
       set (KERNEL_DEFINITIONS "${KERNEL_DEFINITIONS} -march=${RISCV64_OPT}_zvl256b -mabi=lp64d")
     endif()

common_riscv64.h

@@ -89,7 +89,7 @@ static inline int blas_quickdivide(blasint x, blasint y){
 #define BUFFER_SIZE     ( 32 << 20)
 #define SEEK_ADDRESS
 
-#if defined(C910V) || defined(RISCV64_ZVL256B) || defined(RISCV64_ZVL128B) || defined(x280)
+#if defined(C910V) || defined(RISCV64_ZVL1024B) || defined(RISCV64_ZVL256B) || defined(RISCV64_ZVL128B) || defined(x280)
 # include <riscv_vector.h>
 #endif
 
@@ -101,7 +101,7 @@ static inline int blas_quickdivide(blasint x, blasint y){
 #define RISCV_RVV(x) __riscv_ ## x
 #endif
 
-#if defined(C910V) || defined(RISCV64_ZVL256B)
+#if defined(C910V) || defined(RISCV64_ZVL1024B) || defined(RISCV64_ZVL256B)
 # if !defined(DOUBLE)
 #  define EXTRACT_FLOAT(v) RISCV_RVV(vfmv_f_s_f32m1_f32)(v)
 # else

cpuid_riscv64.c

@@ -70,26 +70,29 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 /* or implied, of The University of Texas at Austin.                 */
 /*********************************************************************/
 
-#define CPU_GENERIC         0
-#define CPU_C910V           1
-#define CPU_x280            2
-#define CPU_RISCV64_ZVL256B 3
-#define CPU_RISCV64_ZVL128B 4
-#define CPU_U74             5
+#define CPU_GENERIC          0
+#define CPU_C910V            1
+#define CPU_x280             2
+#define CPU_RISCV64_ZVL1024B 3
+#define CPU_RISCV64_ZVL256B  4
+#define CPU_RISCV64_ZVL128B  5
+#define CPU_U74              6
 
 static char *cpuname[] = {
   "RISCV64_GENERIC",
   "C910V",
   "x280",
-  "CPU_RISCV64_ZVL256B",
-  "CPU_RISCV64_ZVL128B",
+  "RISCV64_ZVL1024B",
+  "RISCV64_ZVL256B",
+  "RISCV64_ZVL128B",
   "U74"
 };
 
 static char *cpuname_lower[] = {
   "riscv64_generic",
   "c910v",
   "x280",
+  "riscv64_zvl1024b",
   "riscv64_zvl256b",
   "riscv64_zvl128b",
   "u74"

docs/install.md

@@ -810,6 +810,7 @@ the resulting build is vectorized.
 | `RISCV64_GENERIC`   | None — scalar reference path   | Non-vector cores, or as a baseline reference build      |
 | `RISCV64_ZVL128B`   | RVV 1.0, VLEN >= 128 bits      | Generic RVV-1.0 hardware with 128-bit vector registers  |
 | `RISCV64_ZVL256B`   | RVV 1.0, VLEN >= 256 bits      | Generic RVV-1.0 hardware with 256-bit vector registers  |
+| `RISCV64_ZVL1024B`  | RVV 1.0, VLEN >= 1024 bits     | Wide-VLEN RVV cores (e.g. SpacemiT K3 A100)             |
 | `C910V`             | RVV 0.7.1 (legacy)             | T-Head C910 (Allwinner D1, etc.)                        |
 | `x280`              | RVV 1.0, SiFive-tuned          | SiFive x280 cores                                       |
 
@@ -820,7 +821,7 @@ scalar `-march` override for this target that takes precedence over any
 user-supplied `-march=rv64gcv` flag, so passing the V extension on the
 command line will not produce a vectorized build under this target.
 
-For RVV 1.0 vectorized builds, use `RISCV64_ZVL128B` or `RISCV64_ZVL256B`.
+For RVV 1.0 vectorized builds, use `RISCV64_ZVL128B`, `RISCV64_ZVL256B`, or `RISCV64_ZVL1024B`.
 These targets route all three BLAS levels including DGEMM to the
 `_rvv.c` kernel set introduced in 2022; see
 [issue #3808](https://github.com/OpenMathLib/OpenBLAS/issues/3808) for the
@@ -830,7 +831,7 @@ codebase separation.
 #### Compiler requirements for ZVL targets
 
 GCC 14 or later is required on current OpenBLAS releases when building the
-`RISCV64_ZVL128B` or `RISCV64_ZVL256B` targets. GCC 13 does not implement
+`RISCV64_ZVL128B`, `RISCV64_ZVL256B`, or `RISCV64_ZVL1024B` targets. GCC 13 does not implement
 the segmented load/store intrinsics (`__riscv_vsseg*`) used by the
 `_rvv.c` kernels; under GCC 13 the build still completes and produces a
 library, but the affected routines fall back to scalar code paths.

driver/others/dynamic_riscv64.c

@@ -113,19 +113,24 @@ unsigned detect_riscv64_get_vlenb(void);
 uint64_t detect_riscv64_rvv100(void);
 
 extern gotoblas_t gotoblas_RISCV64_GENERIC;
+#if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL1024B)
+extern gotoblas_t gotoblas_RISCV64_ZVL1024B;
+#endif
 #if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL256B)
 extern gotoblas_t gotoblas_RISCV64_ZVL256B;
 #endif
 #if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL128B)
 extern gotoblas_t gotoblas_RISCV64_ZVL128B;
 #endif
 
-#define CPU_GENERIC         0
-#define CPU_RISCV64_ZVL256B 1
-#define CPU_RISCV64_ZVL128B 2
+#define CPU_GENERIC          0
+#define CPU_RISCV64_ZVL1024B 1
+#define CPU_RISCV64_ZVL256B  2
+#define CPU_RISCV64_ZVL128B  3
 
 static char *cpuname[] = {
 	"riscv64_generic",
+	"riscv64_zvl1024b",
 	"riscv64_zvl256b",
 	"riscv64_zvl128b"
 };
@@ -135,6 +140,10 @@ extern int openblas_verbose(void);
 extern void openblas_warning(int verbose, const char* msg);
 
 char* gotoblas_corename(void) {
+#if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL1024B)
+	if (gotoblas == &gotoblas_RISCV64_ZVL1024B)
+		return cpuname[CPU_RISCV64_ZVL1024B];
+#endif
 #if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL256B)
 	if (gotoblas == &gotoblas_RISCV64_ZVL256B)
 		return cpuname[CPU_RISCV64_ZVL256B];
@@ -206,6 +215,10 @@ static gotoblas_t* get_coretype(void) {
 
 	if (vlenb < 16)
 		return NULL;
+#if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL1024B)
+	if (vlenb >= 128)
+		return &gotoblas_RISCV64_ZVL1024B;
+#endif
 #if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL256B)
 	if (vlenb >= 32)
 		return &gotoblas_RISCV64_ZVL256B;
@@ -229,6 +242,16 @@ static gotoblas_t* force_coretype(char* coretype) {
 	if (i == CPU_GENERIC)
 		return &gotoblas_RISCV64_GENERIC;
 
+	if (i == CPU_RISCV64_ZVL1024B) {
+#if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL1024B)
+		return &gotoblas_RISCV64_ZVL1024B;
+#else
+		openblas_warning(1,
+				 "riscv64_zvl1024b support not compiled in\n");
+		return NULL;
+#endif
+	}
+
 	if (i == CPU_RISCV64_ZVL256B) {
 #if !defined(DYNAMIC_LIST) || defined(DYN_RISCV64_ZVL256B)
 		return &gotoblas_RISCV64_ZVL256B;

getarch.c

@@ -1840,6 +1840,19 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #else
 #endif
 
+#ifdef FORCE_RISCV64_ZVL1024B
+#define FORCE
+#define ARCHITECTURE    "RISCV64"
+#define SUBARCHITECTURE "RISCV64_ZVL1024B"
+#define SUBDIRNAME      "riscv64"
+#define ARCHCONFIG   "-DRISCV64_ZVL1024B " \
+       "-DL1_DATA_SIZE=64536 -DL1_DATA_LINESIZE=32 " \
+       "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
+       "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
+#define LIBNAME   "riscv64_zvl1024b"
+#define CORENAME  "RISCV64_ZVL1024B"
+#endif
+
 #ifdef FORCE_RISCV64_ZVL256B
 #define FORCE
 #define ARCHITECTURE    "RISCV64"

kernel/generic/neg_tcopy_32.c

@@ -0,0 +1,26 @@
+/*********************************************************************/
+/* Copyright 2025 The OpenBLAS Project.                              */
+/* Bitsliced neg_tcopy MR=32 — panels 32,16,8,4,2,1.                 */
+/*********************************************************************/
+#include "common.h"
+
+int CNAME(BLASLONG m, BLASLONG n, FLOAT *a, BLASLONG lda, FLOAT *b){
+  FLOAT *boffset = b;
+  BLASLONG widths[] = {32, 16, 8, 4, 2, 1};
+  BLASLONG col = 0;
+  int wi;
+
+  for (wi = 0; wi < 6; wi++) {
+    BLASLONG w = widths[wi];
+    while (n >= w) {
+      BLASLONG k, r;
+      for (k = 0; k < m; k++) {
+        for (r = 0; r < w; r++)
+          *boffset++ = -a[(col + r) + k * lda];
+      }
+      col += w;
+      n -= w;
+    }
+  }
+  return 0;
+}

kernel/generic/neg_tcopy_64.c

@@ -0,0 +1,26 @@
+/*********************************************************************/
+/* Copyright 2025 The OpenBLAS Project.                              */
+/* Bitsliced neg_tcopy MR=64 — panels 64,32,16,8,4,2,1.              */
+/*********************************************************************/
+#include "common.h"
+
+int CNAME(BLASLONG m, BLASLONG n, FLOAT *a, BLASLONG lda, FLOAT *b){
+  FLOAT *boffset = b;
+  BLASLONG widths[] = {64, 32, 16, 8, 4, 2, 1};
+  BLASLONG col = 0;
+  int wi;
+
+  for (wi = 0; wi < 7; wi++) {
+    BLASLONG w = widths[wi];
+    while (n >= w) {
+      BLASLONG k, r;
+      for (k = 0; k < m; k++) {
+        for (r = 0; r < w; r++)
+          *boffset++ = -a[(col + r) + k * lda];
+      }
+      col += w;
+      n -= w;
+    }
+  }
+  return 0;
+}

kernel/generic/trsm_kernel_LN.c

@@ -70,6 +70,14 @@ static FLOAT dm1 = -1.;
 #define GEMM_UNROLL_M_SHIFT 4
 #endif
 
+#if GEMM_DEFAULT_UNROLL_M == 32
+#define GEMM_UNROLL_M_SHIFT 5
+#endif
+
+#if GEMM_DEFAULT_UNROLL_M == 64
+#define GEMM_UNROLL_M_SHIFT 6
+#endif
+
 #if GEMM_DEFAULT_UNROLL_N == 1
 #define GEMM_UNROLL_N_SHIFT 0
 #endif

kernel/generic/trsm_kernel_LT.c

@@ -70,6 +70,14 @@ static FLOAT dm1 = -1.;
 #define GEMM_UNROLL_M_SHIFT 4
 #endif
 
+#if GEMM_DEFAULT_UNROLL_M == 32
+#define GEMM_UNROLL_M_SHIFT 5
+#endif
+
+#if GEMM_DEFAULT_UNROLL_M == 64
+#define GEMM_UNROLL_M_SHIFT 6
+#endif
+
 #if GEMM_DEFAULT_UNROLL_N == 1
 #define GEMM_UNROLL_N_SHIFT 0
 #endif