🖥️ Unified vs Split Cache Performance Analysis using RISC-V

A Computer Organization and Architecture (COA) project that compares the performance of Unified Cache and Split Cache architectures using RISC-V Assembly programs executed in the Ripes Simulator.

The project analyzes cache behavior by evaluating instruction and data memory accesses under different cache organizations and compares their performance characteristics.

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📖 Project Overview

Cache memory is a high-speed memory that reduces processor access time by storing frequently used data and instructions.

This project investigates two commonly used cache organizations:

• Unified Cache – A single cache shared by instructions and data.
• Split Cache – Separate caches for instructions (I-Cache) and data (D-Cache).

The implementation was carried out using RISC-V Assembly Language and simulated using the Ripes Simulator to observe cache statistics and compare their performance.

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🎯 Objectives

• Study the architecture of Unified and Split Cache.
• Implement RISC-V Assembly programs.
• Analyze cache performance using the Ripes Simulator.
• Compare cache statistics.
• Understand the impact of cache organization on processor performance.

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🛠️ Technologies Used

• RISC-V Assembly Language
• Ripes Simulator
• Computer Organization & Architecture
• Cache Memory
• Git & GitHub

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👥 Team Project

This project was developed as part of the Computer Organization and Architecture (COA) course.

This repository serves as a portfolio version of the project, containing the implementation, project presentation, documentation, and source code.

Note: This repository is maintained as a portfolio version of the academic project. The original classroom submission was completed as a team project.

📂 Repository Structure

Unified-vs-Split-Cache-RISC-V
│
├── assembly-programs
│   ├── unified-cache.s
│   └── split-cache.s
│
├── screenshots
│   ├── unified-cache-results.png
│   ├── split-cache-instruction-cache.png
│   └── split-cache-data-cache.png
│
├── presentation.pdf
└── README.md

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🚀 How to Run

1. Install the Ripes Simulator.
2. Open either assembly program from the assembly-programs folder.
3. Assemble the program.
4. Enable cache simulation.
5. Execute the program.
6. Observe cache statistics.
7. Compare Unified Cache and Split Cache performance.

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📸 Screenshots

Unified Cache

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Split Cache – Instruction Cache

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Split Cache – Data Cache

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📊 Performance Summary

Unified Cache

• Single cache for both instructions and data.
• Simpler cache organization.
• Instruction and data accesses compete for the same cache space.
• Can experience higher cache contention.

Split Cache

• Separate Instruction Cache and Data Cache.
• Reduced cache contention.
• Independent instruction and data accesses.
• Better cache utilization.
• Improved execution efficiency in many workloads.

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📚 Learning Outcomes

Through this project, I gained practical knowledge of:

• RISC-V Assembly Programming
• Cache Memory Organization
• Computer Architecture Concepts
• Performance Analysis
• Ripes Simulator
• GitHub Documentation

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📄 Project Presentation

The complete project presentation is available in this repository.

File: presentation.pdf

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👩‍💻 Author

Anannya AK

Computer Science and Engineering (Data Science) Student

GitHub: Anannya97

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