From 41a47d5784c47a178c4149161ef4a8631d48c126 Mon Sep 17 00:00:00 2001 From: David Garske Date: Wed, 26 Aug 2026 07:38:30 -0700 Subject: [PATCH] Add STM32V8 (Cortex-M85) hardware crypto family support --- .wolfssl_known_macro_extras | 3 + IDE/STM32Cube/README.md | 1 + IDE/STM32Cube/default_conf.ftl | 11 ++- wolfcrypt/src/port/st/README.md | 1 + wolfcrypt/src/port/st/stm32.c | 118 +++++++++++++++++++++--------- wolfssl/wolfcrypt/port/st/stm32.h | 117 ++++++++++++++++++++++++++--- wolfssl/wolfcrypt/settings.h | 17 ++++- 7 files changed, 219 insertions(+), 49 deletions(-) diff --git a/.wolfssl_known_macro_extras b/.wolfssl_known_macro_extras index db2ab0ae149..e7c08d53e80 100644 --- a/.wolfssl_known_macro_extras +++ b/.wolfssl_known_macro_extras @@ -241,9 +241,11 @@ CRLDP_VALIDATE_DATA CRL_REPORT_LOAD_ERRORS CRL_STATIC_REVOKED_LIST CRYPTOCELL_KEY_SIZE +CRYP_CR_ALGOMODE_0 CRYP_HEADERWIDTHUNIT_BYTE CRYP_KEYIVCONFIG_ONCE CRYP_KEYSIZE_192B +CRYP_SR_KEYVALID CSM_UNSUPPORTED_ALGS CTAO_CRYPT_AES_H CTYPE_USER @@ -1096,6 +1098,7 @@ WOLFSSL_STM32C5 WOLFSSL_STM32F3 WOLFSSL_STM32F427_RNG WOLFSSL_STM32U0 +WOLFSSL_STM32V8 WOLFSSL_STM32_DHUK_UNWRAP WOLFSSL_STM32_USE_SAES WOLFSSL_STRONGEST_HASH_SIG diff --git a/IDE/STM32Cube/README.md b/IDE/STM32Cube/README.md index 20ed0b06ea6..83eaafdbadd 100644 --- a/IDE/STM32Cube/README.md +++ b/IDE/STM32Cube/README.md @@ -102,6 +102,7 @@ The section for "Hardware platform" may need to be adjusted depending on your pr * To enable STM32H5 support define `WOLFSSL_STM32H5`. * To enable STM32MP13 support define `WOLFSSL_STM32MP13`. * To enable STM32N6 support define `WOLFSSL_STM32N6`. +* To enable STM32V8 support define `WOLFSSL_STM32V8` (STM32V873 only; other V8 variants such as V863 have a different peripheral set). To use the STM32 Cube HAL support make sure `WOLFSSL_STM32_CUBEMX` is defined. diff --git a/IDE/STM32Cube/default_conf.ftl b/IDE/STM32Cube/default_conf.ftl index 486f3742669..3e3712bf09f 100644 --- a/IDE/STM32Cube/default_conf.ftl +++ b/IDE/STM32Cube/default_conf.ftl @@ -252,6 +252,15 @@ extern ${variable.value} ${variable.name}; #ifndef HAL_CONSOLE_UART #define HAL_CONSOLE_UART huart1 #endif +#elif defined(STM32V873xx) + #define WOLFSSL_STM32V8 + #define STM32_HAL_V2 + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define WOLFSSL_STM32_PKA + #ifndef HAL_CONSOLE_UART + #define HAL_CONSOLE_UART huart1 + #endif #else #warning Please define a hardware platform! /* This means there is not a pre-defined platform for your board/CPU */ @@ -259,7 +268,7 @@ extern ${variable.value} ${variable.name}; /* CPU Type: WOLFSSL_STM32F1, WOLFSSL_STM32F2, WOLFSSL_STM32F4, WOLFSSL_STM32F7, WOLFSSL_STM32H7, WOLFSSL_STM32L4, WOLFSSL_STM32L5, WOLFSSL_STM32G0, WOLFSSL_STM32G4, WOLFSSL_STM32WB, WOLFSSL_STM32U3, - WOLFSSL_STM32U5 and WOLFSSL_STM32MP13 */ + WOLFSSL_STM32U5, WOLFSSL_STM32V8 and WOLFSSL_STM32MP13 */ #define WOLFSSL_STM32F4 /* Debug UART used for printf */ diff --git a/wolfcrypt/src/port/st/README.md b/wolfcrypt/src/port/st/README.md index 76dcf456aa4..fe5bf228ee2 100644 --- a/wolfcrypt/src/port/st/README.md +++ b/wolfcrypt/src/port/st/README.md @@ -24,6 +24,7 @@ Support for STM32 on-chip crypto hardware acceleration across the following fami | `WOLFSSL_STM32C0` | C0xx (not yet supported in settings.h; SW only) | | `WOLFSSL_STM32C5` | C5xx (TinyAES / HASH / RNG / SAES / V2 PKA sign-only / DHUK / CCB) | | `WOLFSSL_STM32N6` | N6xx (TinyAES / HASH / RNG / SAES / V2 PKA / DHUK; M55 core) | +| `WOLFSSL_STM32V8` | V873 only (CRYP / HASH / RNG / SAES / V2 PKA sign+verify; M85 core) | | `WOLFSSL_STM32MP13` | MP13 (CRYP / HASH / RNG / PKA; Cortex-A7) | | `WOLFSSL_STM32MP25` | MP25 (not yet supported in settings.h; Cortex-A35 + M33) | diff --git a/wolfcrypt/src/port/st/stm32.c b/wolfcrypt/src/port/st/stm32.c index 69aab9deddc..3b1aab8a3ae 100644 --- a/wolfcrypt/src/port/st/stm32.c +++ b/wolfcrypt/src/port/st/stm32.c @@ -100,6 +100,9 @@ #elif defined(WOLFSSL_STM32N6) #include #include +#elif defined(WOLFSSL_STM32V8) +#include +#include #elif defined(WOLFSSL_STM32H5) #include #include @@ -1027,7 +1030,7 @@ static void wc_Stm32_Hash_SaveContext(STM32_HASH_Context* ctx) ctx->HASH_IMR = HASH->IMR; ctx->HASH_STR = HASH->STR; ctx->HASH_CR = HASH->CR; -#ifdef STM32_HASH_SHA3 +#ifdef WC_STM32_HASH_HAS_SHA3CFGR ctx->SHA3CFGR = HASH->SHA3CFGR; #endif for (i=0; iIMR = ctx->HASH_IMR; HASH->STR = ctx->HASH_STR; -#ifdef STM32_HASH_SHA3 +#ifdef WC_STM32_HASH_HAS_SHA3CFGR HASH->SHA3CFGR = ctx->SHA3CFGR; #endif @@ -2295,7 +2298,7 @@ int wc_Stm32_Aes_DhukOp(struct Aes* aes, byte* out, const byte* in, /* ===== Bare-metal direct-register AES driver ===== * No HAL or StdPeriph. Two IP variants: - * - CRYP (FIFO-based): F2/F4/F7/H7/MP13 + * - CRYP (FIFO-based): F2/F4/F7/H7/MP13/V8 * - AES/SAES (TinyAES): L4/L5/U5/H573/G0/G4/WB/WL/WBA/H7S(via SAES) * * H7S3 has both a "fat" CRYP (same register shape as H753) AND a @@ -2303,11 +2306,17 @@ int wc_Stm32_Aes_DhukOp(struct Aes* aes, byte* out, const byte* in, * SAES -- the plain CRYP is gated behind the security domain. The H7S * arm therefore goes through the TinyAES branch with WC_STM32_AES_INST * = SAES (forced via WOLFSSL_STM32_USE_SAES in the per-board settings). + * + * V8 also carries both IPs, but the part always runs Secure and its fat + * CRYP is reachable (unlike N6/H7S), so V8 defaults to the CRYP branch + * (AES-192 capable); WOLFSSL_STM32_USE_SAES routes it through the + * TinyAES branch on the SAES instance instead. * Variant selected via family ifdefs below. */ #if defined(WOLFSSL_STM32F2) || defined(WOLFSSL_STM32F4) || \ defined(WOLFSSL_STM32F7) || defined(WOLFSSL_STM32H7) || \ - defined(WOLFSSL_STM32MP13) + defined(WOLFSSL_STM32MP13) || \ + (defined(WOLFSSL_STM32V8) && !defined(WOLFSSL_STM32_USE_SAES)) /* ----- CRYP IP (FIFO-based) ----- */ #ifndef STM32_BARE_AES_TIMEOUT @@ -2428,18 +2437,63 @@ static int Stm32AesXferBlock(const byte* in, byte* out) return 0; } -/* CBC/ECB decrypt requires a key-prep pass first (per F4/H7 reference manual: - * load key, run ALGOMODE=AES_KEY, wait BUSY=0, then start the actual op). */ -static int Stm32AesPrepareKey(word32 keyLen) +#ifdef CRYP_SR_KEYVALID +/* Key-management CRYP variant (e.g. STM32V8): the engine refuses to + * process data until the loaded key validates (SR.KEYVALID). */ +static int Stm32AesWaitKeyValid(void) { - int ret; + int t = 0; + while ((CRYP->SR & CRYP_SR_KEYVALID) == 0) { + if (++t >= STM32_BARE_AES_TIMEOUT) { + return WC_TIMEOUT_E; + } + } + return 0; +} +#endif - CRYP->CR = CRYP_CR_ALGOMODE_AES_KEY | - STM32_CRYP_DATATYPE_BYTE | - Stm32AesKeySizeBits(keyLen); - CRYP->CR |= CRYP_CR_CRYPEN; - ret = Stm32AesWaitBusy(); - CRYP->CR &= ~CRYP_CR_CRYPEN; +/* Program the CR configuration, load the key, and (for decrypt) run the + * AES key-derivation pass (per F4/H7 reference manual: run ALGOMODE=AES_KEY, + * wait BUSY=0, then start the actual op). + * + * The CR write deliberately happens BEFORE the key registers: on the + * key-management CRYP variant (STM32V8, SR.KEYVALID/KERF) the key is + * latched against the already-programmed KEYSIZE/KMOD and never validates + * -- stalling the engine with a FIFO-wait timeout -- if the key registers + * are written first. The order is harmless on the classic CRYP + * (F2/F4/F7/H7/MP13). Verified on V873 silicon: KEYVALID sets with this + * order and survives both the key-derivation pass and the ALGOMODE-only + * rewrite to the final operating mode. */ +static int Stm32AesSetupKey(const word32* key, word32 keyLen, word32 cr, + int isEnc) +{ + int ret = 0; + + if (!isEnc) { + CRYP->CR = CRYP_CR_ALGOMODE_AES_KEY | + STM32_CRYP_DATATYPE_BYTE | + Stm32AesKeySizeBits(keyLen); + Stm32AesLoadKey(key, keyLen); + #ifdef CRYP_SR_KEYVALID + ret = Stm32AesWaitKeyValid(); + if (ret != 0) { + return ret; + } + #endif + CRYP->CR |= CRYP_CR_CRYPEN; + ret = Stm32AesWaitBusy(); + CRYP->CR &= ~CRYP_CR_CRYPEN; + if (ret == 0) { + CRYP->CR = cr; + } + } + else { + CRYP->CR = cr; + Stm32AesLoadKey(key, keyLen); + #ifdef CRYP_SR_KEYVALID + ret = Stm32AesWaitKeyValid(); + #endif + } return ret; } @@ -2469,21 +2523,16 @@ int wc_Stm32_Aes_Ecb(struct Aes* aes, byte* out, const byte* in, WC_STM32_AES_CLK_ENABLE(); - Stm32AesLoadKey(aes->key, keyLen); - if (!isEnc) { - ret = Stm32AesPrepareKey(keyLen); - if (ret != 0) { - goto exit; - } - } - cr = CRYP_CR_ALGOMODE_AES_ECB | STM32_CRYP_DATATYPE_BYTE | Stm32AesKeySizeBits(keyLen); if (!isEnc) { cr |= CRYP_CR_ALGODIR; } - CRYP->CR = cr; + ret = Stm32AesSetupKey(aes->key, keyLen, cr, isEnc); + if (ret != 0) { + goto exit; + } CRYP->CR |= CRYP_CR_FFLUSH; CRYP->CR |= CRYP_CR_CRYPEN; @@ -2533,22 +2582,17 @@ int wc_Stm32_Aes_Cbc(struct Aes* aes, byte* out, const byte* in, WC_STM32_AES_CLK_ENABLE(); - Stm32AesLoadKey(aes->key, keyLen); - if (!isEnc) { - ret = Stm32AesPrepareKey(keyLen); - if (ret != 0) { - goto exit; - } - } - Stm32AesLoadIV((const byte*)aes->reg, WC_AES_BLOCK_SIZE); - cr = CRYP_CR_ALGOMODE_AES_CBC | STM32_CRYP_DATATYPE_BYTE | Stm32AesKeySizeBits(keyLen); if (!isEnc) { cr |= CRYP_CR_ALGODIR; } - CRYP->CR = cr; + ret = Stm32AesSetupKey(aes->key, keyLen, cr, isEnc); + if (ret != 0) { + goto exit; + } + Stm32AesLoadIV((const byte*)aes->reg, WC_AES_BLOCK_SIZE); CRYP->CR |= CRYP_CR_FFLUSH; CRYP->CR |= CRYP_CR_CRYPEN; @@ -2782,6 +2826,14 @@ int wc_Stm32_Aes_Gcm(struct Aes* aes, byte* out, const byte* in, word32 sz, CRYP->CR = cr_base | (0u << CRYP_CR_GCM_CCMPH_Pos); Stm32AesLoadKey(aes->key, keyLen); +#ifdef CRYP_SR_KEYVALID + /* Key-management CRYP (STM32V8): key latches against the CR config + * written above; wait for it to validate before the init phase. */ + ret = Stm32AesWaitKeyValid(); + if (ret != 0) { + goto exit; + } +#endif /* 12-byte IV || counter=0x00000002 (HW pre-increments to 2 for the * first payload block; init phase sets up J0). */ diff --git a/wolfssl/wolfcrypt/port/st/stm32.h b/wolfssl/wolfcrypt/port/st/stm32.h index c3b63dc4eec..b823c2b43bd 100644 --- a/wolfssl/wolfcrypt/port/st/stm32.h +++ b/wolfssl/wolfcrypt/port/st/stm32.h @@ -297,6 +297,35 @@ WC_STM32_CLK_DIS(AHB3ENR, RCC_AHB3ENR_HASHEN) #define WC_STM32_RNG_CLK_ENABLE() \ WC_STM32_CLK_EN(AHB3ENR, RCC_AHB3ENR_RNGEN) +#elif defined(WOLFSSL_STM32V8) + /* V8 (Cortex-M85), per STM32V873.svd: CRYP + HASH + RNG + SAES + PKA + * on AHB3 bits 0/1/2/3/8 -- same topology as N6, including the "fat" + * CRYP (AES-192 capable, F4/H7 register shape) alongside a TinyAES- + * shape SAES. Unlike N6 (where the CRYP is locked to the security + * domain and AES must route through SAES), the V8 always runs Secure + * and the CRYP is reachable, so the default AES path is the fat CRYP; + * WOLFSSL_STM32_USE_SAES opts into the SAES instance instead (losing + * AES-192). The CCB peripheral (AHB3 bit 15) exists in silicon but is + * not supported (no V8 entry in the WC_STM32_HAS_DHUK / WC_STM32_HAS_CCB + * gates below). */ + #ifdef RCC_AHB3ENR_CRYPEN + #define WC_STM32_AES_CLK_ENABLE() \ + WC_STM32_CLK_EN(AHB3ENR, RCC_AHB3ENR_CRYPEN) + #define WC_STM32_AES_CLK_DISABLE() \ + WC_STM32_CLK_DIS(AHB3ENR, RCC_AHB3ENR_CRYPEN) + #endif + #ifdef RCC_AHB3ENR_SAESEN + #define WC_STM32_SAES_CLK_ENABLE() \ + WC_STM32_CLK_EN(AHB3ENR, RCC_AHB3ENR_SAESEN) + #define WC_STM32_SAES_CLK_DISABLE() \ + WC_STM32_CLK_DIS(AHB3ENR, RCC_AHB3ENR_SAESEN) + #endif + #define WC_STM32_HASH_CLK_ENABLE() \ + WC_STM32_CLK_EN(AHB3ENR, RCC_AHB3ENR_HASHEN) + #define WC_STM32_HASH_CLK_DISABLE() \ + WC_STM32_CLK_DIS(AHB3ENR, RCC_AHB3ENR_HASHEN) + #define WC_STM32_RNG_CLK_ENABLE() \ + WC_STM32_CLK_EN(AHB3ENR, RCC_AHB3ENR_RNGEN) #elif defined(WOLFSSL_STM32H7S) /* H7RS/H7S3: classic H7 fat CRYP + classic H7 HASH (same register * shapes as H753) but RCC clock-enable bits moved to AHB3ENR, and @@ -350,6 +379,24 @@ #endif #endif +/* Named ALGOMODE values for the fat CRYP IP (3-bit field at CR bits 5:3 + * plus the ALGOMODE[3] extension at bit 19 for GCM/CCM; same encoding on + * F2/F4/F7/H7/MP13/V8 per RM0090/RM0433). ST's official CMSIS device + * headers define these named forms; an SVD-generated bare header (e.g. + * STM32V8, where ST publishes no DFP yet) may carry only the raw field + * bits, so provide the named values from those. */ +#if defined(CRYP_CR_ALGOMODE_0) && !defined(CRYP_CR_ALGOMODE_AES_ECB) + #define CRYP_CR_ALGOMODE_AES_ECB (CRYP_CR_ALGOMODE_2) + #define CRYP_CR_ALGOMODE_AES_CBC (CRYP_CR_ALGOMODE_0 | \ + CRYP_CR_ALGOMODE_2) + #define CRYP_CR_ALGOMODE_AES_CTR (CRYP_CR_ALGOMODE_1 | \ + CRYP_CR_ALGOMODE_2) + #define CRYP_CR_ALGOMODE_AES_KEY (CRYP_CR_ALGOMODE_0 | \ + CRYP_CR_ALGOMODE_1 | \ + CRYP_CR_ALGOMODE_2) + #define CRYP_CR_ALGOMODE_AES_GCM (0x00080000UL) /* ALGOMODE[3], bit 19 */ +#endif + /* Companion macro for the IP-instance clock enable. Routes to * WC_STM32_SAES_CLK_ENABLE when WOLFSSL_STM32_USE_SAES is set and the * family arm above provided the SAES variant; otherwise falls back to @@ -462,6 +509,15 @@ do { RCC->AHB3ENR |= RCC_AHB3ENR_PKAEN; (void)RCC->AHB3ENR; } \ while (0) #endif +#elif defined(WOLFSSL_STM32V8) + /* V8: PKA on AHB3 bit 8, V2 layout. PKA_CR.MODE has both 0x24 (sign) and + * 0x26 (verify), so unlike C5/H563 it needs neither _SIGN_ONLY nor + * _VERIFY_ONLY. */ + #ifdef RCC_AHB3ENR_PKAEN + #define WC_STM32_PKA_CLK_ENABLE() \ + do { RCC->AHB3ENR |= RCC_AHB3ENR_PKAEN; (void)RCC->AHB3ENR; } \ + while (0) + #endif #elif defined(WOLFSSL_STM32H7S) /* H7S: PKA on AHB3 alongside HASH/RNG/CRYP/SAES. V2 layout. */ #ifdef RCC_AHB3ENR_PKAEN @@ -478,14 +534,15 @@ * bits) instead of causing a redefinition; otherwise we define our own. */ #if defined(WOLFSSL_STM32H5) || defined(WOLFSSL_STM32MP13) || \ defined(WOLFSSL_STM32N6) || defined(WOLFSSL_STM32H7S) || \ - defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32C5) + defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32C5) || \ + defined(WOLFSSL_STM32V8) /* New-generation HASH IP. The CMSIS struct shape varies within the * family list -- H5 renames the instance digest registers from * `HR[5]` to `HRA[5]`, but U3 / N6 keep the legacy `HR[5]` name * even though the IP otherwise behaves like the new generation. - * Gate the macro on H5 only (verified by inspection of each + * Gate the macro on H5 and V8 (verified by inspection of each * family's CMSIS header). */ - #if defined(WOLFSSL_STM32H5) + #if defined(WOLFSSL_STM32H5) || defined(WOLFSSL_STM32V8) #define WC_STM32_HASH_INSTANCE_HRA #endif /* 4-bit ALGO field at bits 20:17 */ @@ -509,6 +566,25 @@ #define HASH_ALGOSELECTION_SHA512_224 (HASH_CR_ALGO_0 | HASH_CR_ALGO_2 | \ HASH_CR_ALGO_3) #endif + /* SHA-3 ALGO codes 0x4..0x7 (validated against NIST vectors on STM32V8 + * silicon; SHAKE = 0x8/0x9 with a fixed-length squeeze). These fallback + * definitions serve BARE builds of SHA-3-capable parts whose device + * header does not carry the HAL names (MP13 bare today; V8 once its + * SHA-3 context-save procedure is known). CubeMX builds get them from + * the HAL, so the #ifndef guards keep those authoritative. */ + #ifndef HASH_ALGOSELECTION_SHA3_224 + #define HASH_ALGOSELECTION_SHA3_224 HASH_CR_ALGO_2 + #endif + #ifndef HASH_ALGOSELECTION_SHA3_256 + #define HASH_ALGOSELECTION_SHA3_256 (HASH_CR_ALGO_0 | HASH_CR_ALGO_2) + #endif + #ifndef HASH_ALGOSELECTION_SHA3_384 + #define HASH_ALGOSELECTION_SHA3_384 (HASH_CR_ALGO_1 | HASH_CR_ALGO_2) + #endif + #ifndef HASH_ALGOSELECTION_SHA3_512 + #define HASH_ALGOSELECTION_SHA3_512 (HASH_CR_ALGO_0 | \ + HASH_CR_ALGO_1 | HASH_CR_ALGO_2) + #endif #ifndef HASH_ALGOSELECTION_SHA512_256 #define HASH_ALGOSELECTION_SHA512_256 (HASH_CR_ALGO_1 | HASH_CR_ALGO_2 | \ HASH_CR_ALGO_3) @@ -593,7 +669,7 @@ #define STM32_HASH_SHA2 #if defined(WOLFSSL_STM32MP13) || defined(WOLFSSL_STM32H7S) || \ defined(WOLFSSL_STM32N6) || defined(WOLFSSL_STM32H5) || \ - defined(WOLFSSL_STM32U3) + defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32V8) #define HASH_CR_SIZE 103 #define HASH_MAX_DIGEST 64 /* Up to SHA512 */ @@ -608,6 +684,19 @@ #if defined(WOLFSSL_STM32MP13) #define STM32_HASH_SHA3 #endif + /* STM32V8: the HASH block's SHA-3 is real (ALGO codes 0x4..0x7 verified + * against NIST vectors at register level), but wolfSSL's context + * save/restore/copy fails on it -- wolfcrypt_test SHA-3 vector 0 breaks + * at the GetHash/Copy step. MP13 saves SHA3CFGR for this; V8 has no such + * register and its SHA-3 context-switch procedure is not yet known + * (no reference manual). SHA-3 stays software on V8 until it is. */ + #if defined(WOLFSSL_STM32MP13) + /* SHA3CFGR (XOF length) is an MP13 register, not a universal part of + * the SHA-3 capability -- STM32V873.svd has SHA-3 ALGO codes but no + * such register. Gate the context field and its save/restore on this + * rather than on STM32_HASH_SHA3 so other parts still compile. */ + #define WC_STM32_HASH_HAS_SHA3CFGR + #endif #else #define HASH_CR_SIZE 50 #define HASH_MAX_DIGEST 20 @@ -624,7 +713,8 @@ /* These HASH HAL's have no MD5 implementation */ #if defined(WOLFSSL_STM32MP13) || defined(WOLFSSL_STM32H7S) || \ defined(WOLFSSL_STM32N6) || defined(WOLFSSL_STM32H5) || \ - defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32C5) + defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32C5) || \ + defined(WOLFSSL_STM32V8) #define STM32_NOMD5 #endif @@ -653,10 +743,12 @@ /* STM32 register size in bytes */ #define STM32_HASH_REG_SIZE 4 -/* Maximum FIFO buffer is 64 bits for SHA256, 128 bits for SHA512 and 144 bits - * for SHA3 */ +/* FIFO words, sized to the largest rate the HASH IP may accumulate: SHA-256 + * 16, SHA-512 32, SHA3-224 36, SHAKE128 42. Was 36, which is 6 short of + * SHAKE128 -- unreachable while sha3.c forces WC_SHA3_SW_KECCAK for SHAKE, + * but a part with a usable hardware SHAKE would overrun it. */ #if defined(STM32_HASH_SHA3) - #define STM32_HASH_FIFO_SIZE 36 + #define STM32_HASH_FIFO_SIZE 42 #elif defined(STM32_HASH_SHA512) || defined(STM32_HASH_SHA384) #define STM32_HASH_FIFO_SIZE 32 #else @@ -670,7 +762,7 @@ typedef struct { uint32_t HASH_STR; uint32_t HASH_CR; uint32_t HASH_CSR[HASH_CR_SIZE]; -#ifdef STM32_HASH_SHA3 +#ifdef WC_STM32_HASH_HAS_SHA3CFGR uint32_t SHA3CFGR; #endif @@ -741,7 +833,7 @@ struct Aes; defined(WOLFSSL_STM32U5) || defined(WOLFSSL_STM32U3) || \ defined(WOLFSSL_STM32H5) || defined(WOLFSSL_STM32MP13) || \ defined(WOLFSSL_STM32H7S) || defined(WOLFSSL_STM32N6) || \ - defined(WOLFSSL_STM32G0)) + defined(WOLFSSL_STM32V8) || defined(WOLFSSL_STM32G0)) /* Hardware supports AES GCM acceleration */ #define STM32_CRYPTO_AES_GCM #endif @@ -788,7 +880,8 @@ struct Aes; defined(WOLFSSL_STM32H7) || defined(WOLFSSL_STM32U5) || \ defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32H5) || \ defined(WOLFSSL_STM32MP13) || defined(WOLFSSL_STM32H7S) || \ - defined(WOLFSSL_STM32N6) || defined(WOLFSSL_STM32G0)) + defined(WOLFSSL_STM32N6) || defined(WOLFSSL_STM32V8) || \ + defined(WOLFSSL_STM32G0)) #define STM32_HAL_V2 #endif @@ -804,7 +897,7 @@ struct Aes; /* newer crypt HAL requires auth header size as 4 bytes (word) */ #if defined(CRYP_HEADERWIDTHUNIT_BYTE) && \ !defined(WOLFSSL_STM32MP13) && !defined(WOLFSSL_STM32H7S) && \ - !defined(WOLFSSL_STM32N6) + !defined(WOLFSSL_STM32N6) && !defined(WOLFSSL_STM32V8) #define STM_CRYPT_HEADER_WIDTH 1 #else #define STM_CRYPT_HEADER_WIDTH 4 diff --git a/wolfssl/wolfcrypt/settings.h b/wolfssl/wolfcrypt/settings.h index 862c5b13c74..815df24e8ce 100644 --- a/wolfssl/wolfcrypt/settings.h +++ b/wolfssl/wolfcrypt/settings.h @@ -2585,7 +2585,7 @@ defined(WOLFSSL_STM32WL) || defined(WOLFSSL_STM32G4) || \ defined(WOLFSSL_STM32MP13) || defined(WOLFSSL_STM32H7S) || \ defined(WOLFSSL_STM32WBA) || defined(WOLFSSL_STM32N6) || \ - defined(WOLFSSL_STM32C5) + defined(WOLFSSL_STM32C5) || defined(WOLFSSL_STM32V8) #define SIZEOF_LONG_LONG 8 #ifndef CHAR_BIT @@ -2619,6 +2619,13 @@ #if defined(WOLFSSL_STM32N6) && defined(WOLFSSL_STM32_USE_SAES) #define NO_AES_192 #endif + /* STM32V8 has the same arrangement as N6: a "fat" CRYP (K0LR..K3RR, + * CSGCMCCM0..7R, 2-bit KEYSIZE) that does support AES-192, alongside a + * separate TinyAES-shaped SAES instance that does not. Only gate + * NO_AES_192 on routing AES through the SAES. */ + #if defined(WOLFSSL_STM32V8) && defined(WOLFSSL_STM32_USE_SAES) + #define NO_AES_192 + #endif #endif #ifndef NO_STM32_HASH #undef STM32_HASH @@ -2691,11 +2698,13 @@ #endif #elif defined(WOLFSSL_STM32WBA) #include "stm32wbaxx.h" + #elif defined(WOLFSSL_STM32V8) + #include "stm32v8xx.h" #else #error "WOLFSSL_STM32_BARE requires a STM32 family macro \ (e.g. WOLFSSL_STM32F4, WOLFSSL_STM32H5, WOLFSSL_STM32U5, \ - WOLFSSL_STM32N6, ...). Define the matching family flag in \ - user_settings.h." + WOLFSSL_STM32N6, WOLFSSL_STM32V8, ...). Define the matching \ + family flag in user_settings.h." #endif #elif defined(WOLFSSL_STM32_CUBEMX) #if defined(WOLFSSL_STM32F1) @@ -2734,6 +2743,8 @@ #include "stm32c5xx_hal.h" #elif defined(WOLFSSL_STM32N6) #include "stm32n6xx_hal.h" + #elif defined(WOLFSSL_STM32V8) + #include "stm32v8xx_hal.h" #elif defined(WOLFSSL_STM32MP13) /* HAL headers error on our ASM files */ #ifndef __ASSEMBLER__