From 31d089d481657f12e40891fb52fef7344ebe38c1 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Mon, 19 Oct 2026 14:36:49 +0530 Subject: [PATCH] PENDING: arm64: dts: qcom: hamoa-evk: add QPS615 Ethernet overlay Add the hamoa-evk staging overlay for the QPS615 M.2 E-key daughter card. With QPS615 installed, the M.2 E-key slot is occupied by the QPS615 PCIe switch (pci1179,0623) instead of a WLAN chip. Describe the QPS615 PCIe switch topology and the dual TC956X Ethernet functions connected through the downstream port. Add GPIO-based PHY reset handling and disable L0s/L1 ASPM for the QPS615 PCIe path. Signed-off-by: Manikanta Mylavarapu --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/hamoa-evk-staging.dtso | 63 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-evk-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index acbfd39d30afc..119a5a9ee8731 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -631,6 +631,8 @@ dtb-$(CONFIG_ARCH_QCOM) += kodiak-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-staging.dtbo +dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-staging.dtbo + dtb-$(CONFIG_ARCH_QCOM) += purwa-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += glymur-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/hamoa-evk-staging.dtso b/arch/arm64/boot/dts/qcom/hamoa-evk-staging.dtso new file mode 100644 index 0000000000000..02b647b303e38 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-evk-staging.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&pcie4_port0 { + + pci@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + aspm-no-l1; + aspm-no-l0s; + + pci@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + aspm-no-l1; + aspm-no-l0s; + + qps615: pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + aspm-no-l1; + aspm-no-l0s; + + gpio-controller; + #gpio-cells = <2>; + + phy-reset-gpios = <&qps615 0 GPIO_ACTIVE_LOW>; + reset-deassert-us = <221000>; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + aspm-no-l1; + aspm-no-l0s; + + phy-reset-gpios = <&qps615 1 GPIO_ACTIVE_LOW>; + reset-deassert-us = <20000>; + }; + }; + }; +};